1. Field of the Invention
This invention is related to computer systems and, more particularly, to memory management within computer systems.
2. Description of the Related Art
Typically, computer systems include one or more caches to reduce the latency of a processor's access to memory. Generally, a cache may store one or more blocks, each of which is a copy of data stored at a corresponding address in the memory system of the computer system. In cases where a system includes multiple processors, or processing cores, some caches may be exclusive to particular processors, while others are shared. Various benefits of shared levels of cache for multi-core processors and multi-threaded workloads are well-understood. However, for multi-programmed workloads, shared levels of cache can leave significant opportunity for optimization. Multiple programs (e.g., one running on each core) can interact micro-architecturally, although they have no real “relation” to one-another. Each of the programs may have very different requirements on execution resources, memory resources, etc. Consequently, the behavior of one program with respect to a shared cache may negatively impact the operation of another program.
Exclusive cache hierarchies are sometimes used to maximize the utility of cache space on a die and prevent off-chip cache misses. Exclusive cache hierarchies generally refers to those cache systems in which different levels of a cache hierarchy do not contain duplicate information. In contrast to exclusive cache hierarchies, inclusive cache hierarchies may contain multiple copies of a sane cache line. While exclusive cache hierarchies may have various benefits in single-core processor chips, in multi-core chips strict exclusivity may be an impediment to achieving optimal performance on multi-threaded workloads since such workloads exhibit multiple cores accessing shared cache lines.
In view of the above, methods and mechanisms are desired for determining when “exclusive” management versus “shared” management for a given cache line is preferred to improve shared cache replacement decisions.